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24-Bit, 192kHz Stereo ADC
DESCRIPTION
The WM8782 is a high performance, low cost stereo audio ADC designed for recordable media applications. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. WM8782 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode operation or Master mode operation. A stereo 24-bit multibit sigma-delta ADC is used with 128x, 64x or 32x oversampling, according to sample rate. Digital audio output word lengths from 16-24 bits and sampling rates from 8kHz to 192kHz are supported. The device is a hardware controlled device and is supplied in a 20-lead SSOP or 20-lead TSSOP package.
WM8782
FEATURES
* * * * * * * * SNR 102dB (`A' weighted @ 48kHz) THD -90dB (at -1dB) Sampling Frequency: 8 - 192kHz Master or Slave Clocking Mode System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs, 768fs Audio Data Interface Modes - 16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified Supply Voltages - Analogue 2.7 to 5.5V - Digital core: 2.7V to 3.6V 20-lead SSOP or 20-lead TSSOP package
APPLICATIONS
* * * * Recordable DVD Players Personal Video Recorders STB Studio Audio Processing Equipment
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, August 2006, Rev 4.2
Copyright 2006 Wolfson Microelectronics plc
WM8782 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 ABSOLUTE MAXIMUM RATINGS.........................................................................5 THERMAL PERFORMANCE .................................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................. 7
SIGNAL TIMING REQUIREMENTS .......................................................................8
SYSTEM CLOCK TIMING.............................................................................................. 8 AUDIO INTERFACE TIMING - MASTER MODE ........................................................... 8 AUDIO INTERFACE TIMING - SLAVE MODE .............................................................. 9
DEVICE DESCRIPTION.......................................................................................10
INTRODUCTION.......................................................................................................... 10 ADC ............................................................................................................................. 10 ADC DIGITAL FILTER ................................................................................................. 10 DIGITAL AUDIO INTERFACE...................................................................................... 11 POWER DOWN CONTROL......................................................................................... 14 POWER ON RESET .................................................................................................... 14
DIGITAL FILTER CHARACTERISTICS ...............................................................16
ADC FILTER RESPONSES ......................................................................................... 16 ADC HIGH PASS FILTER............................................................................................ 17
APPLICATIONS INFORMATION .........................................................................18
RECOMMENDED EXTERNAL COMPONENTS........................................................... 18 RECOMMENDED EXTERNAL COMPONENTS VALUES............................................ 18
PACKAGE DIMENSIONS ....................................................................................19 IMPORTANT NOTICE ..........................................................................................21
ADDRESS:................................................................................................................... 21
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WM8782
PIN CONFIGURATION
MCLK DOUT LRCLK DGND DVDD BCLK IWL FSAMPEN FORMAT VMID 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 M/S AINL AINOPL COM AINR AINOPR AGND AVDD VREFP VREFGND
ORDERING INFORMATION
DEVICE WM8782SEDS WM8782SEDS/R WM8782GEDT WM8782GEDT/R Note: Reel quantity = 2,000 TEMPERATURE RANGE -25C to +85C -25C to +85C -25C to +85C -25C to +85C PACKAGE 20-lead SSOP (Pb-free) 20-lead SSOP (Pb-free, tape and reel) 20-lead TSSOP (Pb-free) 20-lead TSSOP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260oC 260 C 260oC 260oC
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WM8782 PIN DESCRIPTION
PIN NO. 1 2 3 4 5 6 7 NAME MCLK DOUT LRCLK DGND DVDD BCLK IWL TYPE Digital Input Digital Output Digital Input / Output Supply Supply Digital Input / Output Digital Tristate Input Master Clock ADC Digital Audio Data Audio Interface Left / Right Clock Digital Negative Supply Digital Positive Supply Audio Interface Bit Clock Word Length 0 = 16 bit 1 = 20 bit Z = 24 bit Fast Sampling Rate Enable 0 = 48ken 1= 96ken Z= 192ken Audio Mode Select 0 = RJ 1 = LJ Z = I2S Midrail Voltage Decoupling Capacitor Negative Supply and Substrate Connection DESCRIPTION
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8
FSAMPEN
Digital Tristate Input
9
FORMAT
Digital Tristate Input
10 11 12 13 14 15 16 17 18 19 20
VMID VREFGND VREFP AVDD AGND AINOPR AINR COM AINOPL AINL M/S
Analogue Output Supply Analogue Output Supply Supply Analogue Output Analogue Input Analogue Input Analogue Output Analogue Input Digital Input
Positive Reference Voltage Decoupling Pin; 10uF external decoupling Analogue Positive Supply Analogue Negative Supply and Substrate Connection Right Channel Internal Op-Amp Output Right Channel Input Common mode high impedance input should be set to midrail. Left Channel Internal Op-Amp Output Left Channel Input Interface Mode Select 0 = Slave mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs) 1 = Master mode (256fs, 128fs) (fs=word clock frequency)
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WM8782
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Ambient temperature (supplies applied) Storage temperature Pb free package body temperature (reflow 10 seconds) Package body temperature (soldering 2 minutes) Notes 1. Analogue and digital grounds must always be within 0.3V of each other. MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -55C -65C MAX +4.5V +7V DVDD + 0.3V AVDD +0.3V +125C +150C +260C +183C
THERMAL PERFORMANCE
PARAMETER SSOP-20 package Thermal resistance - junction to ambient TSSOP-20 package Thermal resistance - junction to ambient Notes 1. 2. Figure given for package mounted on 4-layer FR4 according to JESD51-7. (No forced air flow is assumed). Thermal performance figures are estimated. SYMBOL TEST CONDITIONS MIN TYP 81 See note 1 72 See note 1 MAX UNIT C/W
RJA
RJA
C/W
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Operating temperature range Notes 1. Digital supply DVDD must never be more than 0.3V greater than AVDD. SYMBOL DVDD AVDD DGND,AGND TA -25 TEST CONDITIONS MIN 2.7 2.7 0 +85 TYP MAX 3.6 5.5 UNIT V V V C
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WM8782 ELECTRICAL CHARACTERISTICS
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Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER ADC Performance Full Scale Input Signal Level (for ADC 0dB Input) Input resistance, using recommended external resistor network on p17. Input capacitance Signal to Noise Ratio (see Terminology note 1,2,4) SNR A-weighted, @ fs = 48kHz Unweighted, @ fs = 48kHz A-weighted, @ fs = 48kHz, AVDD = 3.3V Signal to Noise Ratio (see Terminology note 1,2,4) SNR A-weighted, @ fs = 96kHz Unweighted, @ fs = 96kHz A-weighted, @ fs = 96kHz, AVDD = 3.3V Total Harmonic Distortion THD 1kHz, -1dB Full Scale @ fs = 48kHz 1kHz, -1dB Full Scale @ fs = 96kHz 1kHz, -1dB Full Scale @ fs = 192kHz Dynamic Range Channel Separation (see Terminology note 4) Channel Level Matching Channel Phase Deviation Power Supply Rejection Ratio Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Input leakage current - digital pad Input leakage current - digital tristate input (Note 3) Input capacitance Output LOW Output HIGH Analogue Reference Levels Midrail Reference Voltage Potential Divider Resistance Buffered Reference Voltage VREF source current VREF sink current VMID RVMID VREFP IVREF IVREF -4% AVDD to VMID and VMID to VREFN -4% AVDD/2 50 AVDD/2 +4% 5 5 +4% V k V mA mA VOL VOH IOL=1mA IOH= -1mA 0.9 x DVDD VIL VIH 2.0 -1 0.2 85 5 0.1 x DVDD +1 0.8 V V A A pF V V PSRR DNR -60dBFS 1kHz Input 1kHz signal 1kHz signal 1kHz 100mVpp, applied to AVDD, DVDD 93 93 93 1.0 10 Vrms k SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
20 102 100 100
pF dB dB dB
99 99 99
dB dB dB
-91 -91 -90 102 90 0.1 0.0001 50
dB dB dB dB dB dB Degree dB
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WM8782
Test Conditions DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode unless otherwise stated. PARAMETER Supply Current Analogue supply current Digital supply current Power Down AVDD = 5V DVDD = 3.3V 32 5 0.5 mA mA mA SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Notes: 1. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect dynamic specification values. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce performance. This high leakage current is due to the topology of the instate pads. The pad input is connected to the midpoint of an internal resistor string to pull input to vmid if undriven.
2. 3.
TERMINOLOGY
1. Signal-to-noise ratio (dB) - Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
2.
3. 4.
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WM8782 SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
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Figure 1 System Clock Timing Requirements
Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25 C, fs = 48kHz, Slave Mode, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK duty cycle Table 1 Master Clock Timing Requirements TMCLKL TMCLKH TMCLKY TMCLKDS 11 11 28 40:60 60:40 ns ns ns SYMBOL MIN TYP MAX UNIT
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AUDIO INTERFACE TIMING - MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface)
Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge DOUT propagation delay from BCLK falling edge Table 2 Digital Audio Data Timing - Master Mode tDL tDDA 0 0 10 10 ns ns SYMBOL MIN TYP MAX UNIT
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WM8782
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode
Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low LRCLK set-up time to BCLK rising edge LRCLK hold time from BCLK rising edge DOUT propagation delay from BCLK falling edge Table 3 Digital Audio Data Timing - Slave Mode Note: LRCLK should be synchronous with MCLK, although the WM8782 interface is tolerant of phase variations or jitter on these signals. tBCY tBCH tBCL tLRSU tLRH tDD 50 20 20 10 10 0 10 ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8782 DEVICE DESCRIPTION
INTRODUCTION
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The WM8782 is a stereo 24-bit ADC designed for demanding recording applications such as DVD recorders, studio mixers, PVRs, and AV amplifiers. The WM8782 consists of stereo line level inputs, followed by a sigma-delta modulator and digital filtering. The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes (left justified, right justified or I2S) . An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets. The WM8782 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow Slave mode or Master mode operation. The WM8782 supports master clock rates from 128fs to 768fs and digital audio output word lengths from 16-24 bits. Sampling rates from 8kHz to 192kHz are supported, delivering high SNR operating with 128x, 64x or 32x over-sampling, according to the sample rate. The line inputs are biased internally through the operational amplifier to VMID.
ADC
The WM8782 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is illustrated in Figure 4 Multi-Bit Oversampling Sigma Delta ADC Schematic.
LIN/RIN
ANALOG INTEGRATOR
TO ADC DIGITAL FILTERS
MULTI BITS
Figure 4 Multi-Bit Oversampling Sigma Delta ADC Schematic The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any input voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input has a linear relationship with AVDD. The internal op-amp and appropriate resistors can be used to reduce signals greater than 1Vrms before they reach the ADC. The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface.
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter. The high-pass filter response detailed in Digital Filter Characteristics. The operation of the high pass filter removes residual DC offsets that are present on the audio signal.
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WM8782
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins: * * * DOUT: ADC data output LRCLK: ADC data alignment clock BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always an output. BCLK and LRCLK maybe an inputs or outputs depending whether the device is in Master or Slave mode. (see Master and Slave Mode Operation, below). Three different audio data formats are supported: * * * Left justified Right justified I 2S
MASTER AND SLAVE MODE OPERATION
The WM8782 can be configured as either a master or slave mode device. As a master device the WM8782 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT. In slave mode, the WM8782 responds with data to clocks it receives over the digital audio interface. The mode can be selected by setting the MS input pin (see Table 4 Master/Slave selection below). Master and slave modes are illustrated below.
Figure 5 Master Mode
Figure 6 Slave Mode
PIN M/S
DESCRIPTION Master/Slave Selection 0 = Slave Mode 1= Master Mode
Table 4 Master/Slave selection
AUDIO INTERFACE CONTROL
The Input Word Length and Audio Format mode can be selected by using IWL and FORMAT pins. PIN IWL DESCRIPTION Word Length 0 = 16 bit 1 = 20 bit Z = 24 bit Audio Mode Select 0 = RJ 1 = LJ Z = I2S
FORMAT
Table 5 Audio Data Format Control
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WM8782
AUDIO DATA FORMATS
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In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 7 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 8 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 9 I2S Audio Interface (assuming n-bit word length)
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Production Data MASTER CLOCK AND AUDIO SAMPLE RATES
WM8782
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock (MCLK). The external master system clock can be applied directly through the MCLK input pin. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8782 supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio sampling frequency (LRCLK). In Slave Mode, the WM8782 automatically detects the audio sample rate. In Master Mode, LRCLK is generated for rate 256fs, unless the user changes this to 128fs using the FSAMPEN pin = z (see Table 7 below). BCLK is also generated in Master Mode. BCLK=MCLK/4 for 256fs, and BCLK=MCLK/2 for 128fs. Table 6 shows the common MCLK frequencies for different sample rates. SAMPLING RATE (LRCLK) 8kHz 16kHz 32kHz 44.1kHz 48kHz 96kHz 192kHz Master Clock Frequency (MHz) 128fs 1.024 2.048 4.096 5.6448 6.144 12.288 24.576 192fs 1.536 3.072 6.144 8.467 9.216 18.432 36.864 256fs 2.048 4.096 8.192 11.2896 12.288 24.576 384fs 3.072 6.144 12.288 16.9340 18.432 36.864 512fs 4.096 8.192 16.384 22.5792 24.576 768fs 6.144 12.288 24.576 33.8688 36.864 -
Table 6 Master Clock Frequency Selection In Slave mode, the WM8782 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available (768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8782 is tolerant of phase variations or jitter on these clocks. The WM8782 can operate at sample rates from 8kHz to 192kHz. The WM8782 uses a sigma-delta modulator that operates at a fixed frequency of 6.144MHz (128 x LRCLK oversampling @ 48kHz sampling rate). For correct operation of the device and optimal performance, the user must set the appropriate ADC modulator sampling rate enable. In both Master and Slave Modes, it is recommended that for 96kHz the user sets FSAMPEN to 1, and for 192kHz set FSAMPEN to z. For Master Mode 192kHz, FSAMPEN set to z is a requirement.
PIN M/S
DESCRIPTION Master/Slave Selection 0 = Slave Mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs) 1= Master Mode (256fs, 128fs when FSAMPEN=z) Fast sampling rate enable 0 = 48ken (128x OSR) 1= 96ken (64x OSR) z= 192ken (32x OSR)
FSAMPEN
Table 7 Master/Slave and Sampling Rate Enable Selection
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WM8782
POWER DOWN CONTROL
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The WM8782 can be powered down by stopping MCLK. Power down mode using MCLK is entered after 65536/fs clocks. On power-up, the WM8782 applies the power-on reset sequence described below. When MCLK is stopped DOUT is forced to zero.
POWER ON RESET
Figure 10 Power Supply Timing Requirements - power-on
Figure 11 Power Supply Timing Requirements - power-down
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Production Data Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = DGND = 0V, TA = +25C PARAMETER DVDD level to activate POR - power on AVDD level to activate POR - power on VMID level to activate POR - power on DVDD level to release POR - power on (see notes 1 and 2) AVDD level to release POR - power on (see notes 1 and 2) VMID level to release POR - power on (see notes 1 and 2) POR active period (see notes 1 and 2) DVDD level to activate POR - power off (see note 5) AVDD level to activate POR - power off (see note 5) VMID level to activate POR - power off (see note 5) Power on - POR propagation delay through device Power down - POR propagation delay through device Notes: 1. 2. 3. 4. SYMBOL Vpora Vpora Vpora Vporr Vporr Vporr tpor Vpor_off Vpor_off Vpor_off tpon tpoff TEST CONDITIONS Measured from DGND Measured from AGND Measured from AGND Measured from DGND Measured from AGND Measured from AGND Measured from POR active to POR release Measured from DGND Measured from AGND Measured from AGND Measured from rising EDGE of POR Measured from falling EDGE of POR 30 (note 6) MIN TYP 0.7 0.7 0.7 DVDD Min AVDD Min 1 Defined by DVDD/AVDD/ VMID Rise Time 0.8 0.8 0.7 30 30 MAX
WM8782
UNIT V V V V V V s V V V s s
Power Supply Input Timing Information
5. 6.
POR is activated when DVDD or AVDD or VMID reach their stated Vpora level (Figure 10). POR is only released when DVDD and AVDD and VMID have all reached their stated Vporr levels (Figure 10). The rate of rise of VMID depends on the rate of rise of AVDD, the internal 50k resistance and the external decoupling capacitor. Typical tolerance of 50K resistor can be taken as +/-20%. If AVDD, DVDD or VMID suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpor_off,), then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. The chip will enter reset at power down when AVDD or DVDD or VMID falls below Vpor_off. This may be important if the supply is turned on and off frequently by a power management system. The minimum tpor period is maintained even if DVDD, AVDD and VMID have zero rise time. This specification is guaranteed by design rather than test.
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WM8782 DIGITAL FILTER CHARACTERISTICS
The WM8782 digital filter characteristics scale with sample rate.
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PARAMETER Passband Passband Ripple Stopband Stopband Attenuation Group Delay
TEST CONDITIONS +/- 0.01dB -6dB
MIN 0
TYP
MAX 0.4535fs
UNIT
ADC Sample Rate (Single Rate - 48Hz typically) 0.4892fs +/- 0.01 0.5465fs f > 0.5465fs -65 22 +/- 0.01dB -6dB Passband Ripple Stopband Stopband Attenuation Group Delay Table 8 Digital Filter Characteristics f > 0.5465fs 0.5465fs -65 22 dB fs 0 0.4892fs +/- 0.01 dB 0.4535fs dB fs dB
ADC Sample Rate (Dual Rate - 96kHz typically) Passband
ADC FILTER RESPONSES
0.02
0
0.015 0.01
-20
Response (dB)
Response (dB)
0.005 0 -0.005 -0.01 -0.015 -0.02
-40
-60
-80
0
0.5
1
1.5 Frequency (Fs)
2
2.5
3
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 12 Digital Filter Frequency Response
Figure 13 ADC Digital Filter Ripple
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WM8782
ADC HIGH PASS FILTER
The WM8782 has a digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H(z) =
1 - z-1 1 - 0.9995z-1
0
Response (dB)
-5
-10
-15
0
0.0005
0.001 Frequency (Fs)
0.0015
0.002
Figure 14 ADC Highpass Filter Response
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WM8782 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
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Figure 15 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C8 C2 and C7 C5 and C6 R1 R2 and R5 R3 and R6 R4 C4 C3 C9 C10 SUGGESTED VALUE 10F 0.1F 10F 10k 10k 5k 3.3k 0.1F 10F 0.1F 10F Reference de-coupling capacitors for VREFP pin DESCRIPTION De-coupling for DVDD and AVDD De-coupling for DVDD and AVDD Analogue input AC coupling caps Current limiting resistors Internal op-amp input resistor Internal op-amp feedback resistor Common mode resistor Reference de-coupling capacitors for VMID pin
Table 9 External Components Description
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WM8782
PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) DM0015.C
b
20
e
11
E1
E
1
10
GAUGE PLANE
D
A A2
A1 -C0.10 C
SEATING PLANE
c
L L1
0.25
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----7.20 0.65 BSC 7.80 5.30 0.75 1.25 REF o 4 JEDEC.95, MO -150
MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8782
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
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DM008.D
b
20
e
11
E1
E
GAUGE PLANE 1 10
D 0.25 c A A2 A1 -C0.1 C
SEATING PLANE
L
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 6.40
4.30 0.45 0o
Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153
MAX 1.20 0.15 1.05 0.30 0.20 6.60
4.50 0.75 8o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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Production Data
WM8782
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
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ADDRESS:
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Tel :: +44 (0)131 272 2000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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PD, August 2006, Rev 4.2 21

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